1. Field of Invention
The present invention relates to Direct Digital Frequency Synthesizers (DDS), and more particularly to a DDS based synthesizer architecture allowing, at low price and low complexity, for substantially reduced output spurious level without trading-off the DDS advantages of high frequency resolution and fast settling time.
2. Description of the Related Art
Direct Digital Frequency Synthesis is a digital technique of frequency synthesis providing the advantages of digital control of frequency and phase, high frequency resolution and fast settling time while maintaining a phase coherent output and small size due to monolithic fabrication techniques. However, this technique, in its present form, exhibits relatively poor output spectral quality, mainly evidenced by the presence of numerous spurious signals (commonly referred to as "spurs").
An apparatus employing this technique is referred to as a Direct Digital Synthesizer (DDS). It includes three principal blocks: Accumulator, Look Up Table (LUT) ROM and Digital to Analog Converter (DAC). Depending on the implementation a DDS based Synthesizer may use one, two or three monolithic chips. In most cases the two chips solution is used: one chip consisting of an Accumulator and a LUT ROM (usually called DDS) provides digital samples of the synthesized waveform and a second chip--DAC converts the digital samples to an analog form.
A DDS accumulator converts frequency setting data into phase samples which in turn determine the magnitude of a synthesized output waveform at a given sample time. Consecutive phase samples address a LUT which transforms each phase sample into a digital amplitude sample of a desired (usually sine wave) signal. Digital amplitude samples are converted to an analog form by a DAC and then filtered by an output filter. The spectral purity of the DDS synthesizer is mainly determined by the following elements: (a) truncation of the phase accumulator output applied to the LUT; (b) DAC's resolution; (c) DAC's dynamic performance and (d) alias images. Furthermore, the spectral purity of the synthesized output signal depends on: (e) jitter level of a reference clock and ratio of the synthesized output frequency to the reference clock frequency; (f) DAC's linearity and (g) noise floor of the DDS digital circuitry.
The resulting spurious signals are more or less "randomly" distributed throughout the output frequency range and cannot be removed by filtering.
Spurs due to the phase truncation
The accumulator is a N-bit digital phase integrator. The input frequency word determines the phase step size by which the accumulator is incremented, its output sum represents an instantaneous phase of the synthesized signal (sinewave). The rate of overflow of the accumulator determines an output frequency.
Most integrated solutions for DDS provide an accumulator with typically N=32 bits of resolution, and provision to increase resolution by cascading them. However, the phase-to-sine conversion circuit (Look Up Table), being optimized for cost and power, usually takes only the M most significant bits of the phase accumulator output. This phase truncation introducers jitter in an output waveform, which is observed as spurious Phase Modulation (PM) components. The level of the worst case spur signal due to the phase truncation is equal to: EQU S.sub.PM =-6.multidot.M[dBc].
Quantization Noise
Amplitude quantization also causes spurious responses. As a quantized DDS output waveform is deterministic and periodic, the quantization errors are correlated to the output and not random but rather periodic. As a result, the quantization noise power is not equally spread over the Nyquist bandwidth but concentrated in few discrete Amplitude Modulation (AM) components. These strongly limit the theoretical DAC's Spurs Free Dynamic Range (SFDR). Three limiting cases of the quantization spurs may be considered: (a) there is no close-in common multiple between the DDS clock frequency and the output frequency. In this case the quantization errors have very long period and broad, quite uniformly distributed spectrum, being similar to the white noise floor. In reality, this "noise floor" is rather a "sea" of discrete AM spurious components of relatively similar amplitudes; (b) there is a close-in common multiple between a DDS clock frequency and an output frequency. In this case a quantization "noise" energy is concentrated in several discrete AM spurs due to the highly periodic nature of the error process. Their frequency locations, fixed for a given f.sub.Clk /f.sub.out ratio, will change as the f.sub.out changes, resulting in a random-like spurs pattern at the output; (c) the DDS clock frequency is an integer multiple of the output frequency: ##EQU1## where n=3, 4, 5, 6, . . . . In this case, quantization error AM spurs are harmonically related to the output frequency appearing as its 2.sup.nd, 3.sup.rd, 4.sup.th, . . . etc. harmonics. As a result a "close-in" band (octave) is spurs free.
DAC Time Domain Performance
The DAC's dynamic performance during input code-to code transitions is also a factor determining the DDS output spectral purity (Analog Devices AN-273: "Choosing DACs for Direct Digital Synthesis" by D. Buchanan). The slew rate, output stage balance, glitch pulse, settling time and clock & data feedthroughs, particularly at high sampling rates are the sources of unwanted energy (spurs & noise) spread over the output bandwidth. In general, less samples per period of a synthesized output signal, results in less unwanted energy spread over the output bandwidth and higher output spectral purity.
Spurious due to the Clock
A DDS synthesizer acts as a clock divider with division ratio equal to: ##EQU2## where: ##EQU3## is a selected phase step and a.sub.i is the i.sup.th coefficient of the frequency setting word taking value of 0 or 1.
As a result, the input clock jitter (discrete spurious side-lobes and noise) is attenuated by 20 log(n ). Practically, the DDS output frequency is limited to 1/3 of the clock frequency, to avoid aliasing, so the jitter content of the synthesized output signal is improved by at least 9.5 dB compared to that of the input clock. The lower the output frequency, the higher is the division ratio "n" and the higher the input clock jitter attenuation.
Alias Images
The sampling process modifies the spectrum of the original synthesized signal X(f) by introducing weighted alias images, according to the following equation ##EQU4## ##EQU5## is a sampling frequency, d.sub..epsilon. (t)=1/.epsilon. for .vertline.t.vertline..ltoreq..epsilon. and 0 elsewhere is the idealized sampling pulse and X(f) is the spectrum of the sampled signal.
The sampling process has several consequences: (a) as the output frequency f.sub.out increases, the frequency of the 1.sup.st alias image equal to f.sub.Clk -f.sub.out decreases. This limits the practically achievable maximum f.sub.out to approximately 1/3 of f.sub.Clk due to the limited sharpness of the filters. Much more critical than the 1.sup.st alias image (which may be filtered out) is the harmonic distortion of the synthesized output. The harmonics are usually the predominant source of spurs. They can be easily filtered out in any analog system using octave filters. However in the sampled system, the harmonic images (and their PM spurs) move in the opposite direction to the fundamental output, so they cross over and share the same bandwidth and, therefore, they cannot be removed by filtering; (b) the alias images (1.sup.st, 2.sup.nd . . . etc.) may be considered as the naturally (due to the sampling) upconverted outputs and used after appropriate bandpass filtering. However, in general their spurs free dynamic range is lower than that of the fundamental component. That is why under normal circumstances, fundamental output images cannot be used as the "clean" signal source.
Existing Reduced Spurs DDS Solutions
The described sources of spurious signals are inevitably related to the digital synthesis technique and more particularly to technological limits such as: (a) LUT dimensions (capacity of the fast access memory & its DC power requirement); (b) DAC's effective resolution, dynamic performance & linearity and (c) Sampling process (cross-over alias images generation).
The existing solutions in general consist in randomization of PM and/or AM spurs spectrum. The Essenwanger method, as described in U.S. Pat. No 4,951,237 "Direct Digital Synthesizer with Selectably Randomized Accumulator" randomizes the DDS accumulator overflow by dithering the accumulator's bits. The randomizer adds random or pseudorandom values to a selectable few of the least significant bits of the accumulator to introduce flat or nearly flat frequency deviation density in the vicinity of significant spurs for spurious frequency suppression. This frequency deviation density at the spurs offset from the carrier spreads the energy of the spurs, therefore reducing their level.
The Wilson technique ("Spurious Reduction Techniques for Direct Digital Synthesis"; M. P. Wilson and T. C. Tozer, IEE Digest 1991/172, IEE Colloquium on "Direct Digital Frequency Synthesis", 19 Nov. 1991), for which a patent has been applied, consists in DAC transfer function decorrelation. Pseudo-random numbers are added or subtracted to the LUT output by means of the ALU placed at the digital port of the DAC. By the analogue subtraction of a compensating signal from a second DAC, the output signal is restored to the correct level. As the DAC dithering is random, quantization errors will therefore not correlate between cycles, leading to "noise-like" corresponding AM spurs.
The above mentioned techniques have the following limitations: (a) the improvement of the spectral purity is substantial only for DDSs using the low resolution DACs (practically no more than 8 bits); there is no noticeable improvement with 10 bits DACs (Qualcomm Q2334 with patented Noise Reduction Circuit as an example); (b) the level of spurs is reduced at low sample rates and increases at higher sample rates, so the very important upper range of the DDS Synthesizer output bandwidth is still significantly affected by spurs; (c) if dither is introduced it increases the output phase noise floor; (d) the required hardware is complex, especially for high frequency DDS synthesizers; (e) "in-band" crossover spurs (harmonics alias images) are still a predominant factor limiting the output spectral purity. The Fobbester method ("Spur Reduction in Direct Digital Synthesis" I. Fobbester, Electronic Product Design, June 1992 pp.23-24) uses a "mix-and-divide" technique. The output of the Plessey SP2002 DDS is subsequently upconverted, divided by fixed modulus divider (SP8804 divider by 4) and band-pass filtered. Spurs level reduction is a result of the division process (PM spurs reduced by 20log (Division Ratio), and the hardlimiting process (AM spurs). The Fobbester technique provides a synthesizer system with very limited output bandwidth (in the mentioned system only 2 MHz). This is due to (a) very high level of harmonics produced by FF-based dividers and practically achievable Band Pass Filter (BPF) suppression; (b) limited number of "usable" division ratios generating the 50% duty cycle output signal required to reduce the second harmonic content; c) complex hardware.